Single Wire Protocol Master Interface (SWPMI) RM0351
1500/1830 DocID024597 Rev 5
In the SWPMI interrupt routine, the user must check TXBEF bit in the SWPMI_ISR register.
If it is set, the user must set CTXBEF bit in SWPMI_ICR register to clear TXBEF flag and the
user can update buffer1 in the RAM memory.
In the next SWPMI interrupt routine occurrence, the user will update buffer2, and so on.
The Software can also read the DMA counter (number of data to transfer) in the DMA
registers in order to retrieve the frame which has already been transferred from the RAM
memory and transmitted. For example, if the software works with 4 transmission buffers,
and if the DMA counter equals 17, it means that two buffers are ready for updating in the
RAM area. This is useful in case several frames are sent before the software can handle the
SWPMI interrupt. If this happens, the software will have to update several buffers.
When there are no more frames to transmit, the user must disable the circular mode in the
DMA module. The transmission will stop at the end of the buffer4 transmission.
If the transmission needs to stop before (for example at the end of buffer2), the user must
set the low significant byte of the first word to 0 in buffer3 and buffer4.
TXDMA bit in the SWPMI_CR register will be cleared by hardware as soon as the number of
data bytes in the payload is read as 0 in the least significant byte of the first word.
Figure 482. SWPMI Multi software buffer mode transmission
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