Quad-SPI interface (QUADSPI) RM0351
472/1830 DocID024597 Rev 5
17 Quad-SPI interface (QUADSPI)
17.1 Introduction
The QUADSPI is a specialized communication interface targeting single, dual or quad SPI
Flash memories. It can operate in any of the three following modes:
• indirect mode: all the operations are performed using the QUADSPI registers
• status polling mode: the external Flash memory status register is periodically read and
an interrupt can be generated in case of flag setting
• memory-mapped mode: the external Flash memory is mapped to the microcontroller
address space and is seen by the system as if it was an internal memory
Both throughput and capacity can be increased two-fold using dual-flash mode, where two
Quad-SPI Flash memories are accessed simultaneously.
17.2 QUADSPI main features
• Three functional modes: indirect, status-polling, and memory-mapped
• Dual-flash mode, where 8 bits can be sent/received simultaneously by accessing two
Flash memories in parallel.
• SDR and DDR support
• Fully programmable opcode for both indirect and memory mapped mode
• Fully programmable frame format for both indirect and memory mapped mode
• Integrated FIFO for reception and transmission
• 8, 16, and 32-bit data accesses are allowed
• DMA channel for indirect mode operations
• Interrupt generation on FIFO threshold, timeout, operation complete, and access error
17.3 QUADSPI implementation
This manual describes the full set of features implemented in QUADSPI peripheral.
The Table 98 describes the feature differences for each of the STM32L4xx categories.
Table 98. QUADSPI implementation
(1)
1. X = supported
QUADSPI features STM32L496xx/4A6xx devices
STM32L475xx/476xx/486xx
devices
Dual-flash mode X -
DHHC (DDR hold) X -
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