DocID024597 Rev 5 393/1830
RM0351 Nested vectored interrupt controller (NVIC)
409
13.3 Interrupt and exception vectors
The grey rows in Table 57 describe the vectors without specific position.
Table 57. STM32L4x5/STM32L4x6 vector table
Position
Priority
Type of
priority
Acronym Description Address
- - - - Reserved 0x0000 0000
- -3 fixed Reset Reset 0x0000 0004
- -2 fixed NMI
Non maskable interrupt. The RCC Clock
Security System (CSS) is linked to the NMI
vector.
0x0000 0008
- -1 fixed HardFault All classes of fault 0x0000 000C
- 0 settable MemManage Memory management 0x0000 0010
- 1 settable BusFault Pre-fetch fault, memory access fault 0x0000 0014
- 2 settable UsageFault Undefined instruction or illegal state 0x0000 0018
- - - - Reserved
0x0000 001C -
0x0000 0028
- 3 settable SVCall System service call via SWI instruction 0x0000 002C
- 4 settable Debug Monitor 0x0000 0030
- - - - Reserved 0x0000 0034
- 5 settable PendSV Pendable request for system service 0x0000 0038
- 6 settable SysTick System tick timer 0x0000 003C
0 7 settable WWDG Window Watchdog interrupt 0x0000 0040
1 8 settable PVD_PVM
PVD/PVM1/PVM2/PVM3/PVM4 through EXTI
lines 16/35/36/37/38 interrupts
0x0000 0044
2 9 settable
RTC_TAMP_STAMP
/CSS_LSE
RTC Tamper or TimeStamp /CSS on LSE
through EXTI line 19 interrupts
0x0000 0048
3 10 settable RTC_WKUP
RTC Wakeup timer through EXTI line 20
interrupt
0x0000 004C
4 11 settable FLASH Flash global interrupt 0x0000 0050
5 12 settable RCC RCC global interrupt 0x0000 005C
6 13 settable EXTI0 EXTI Line0 interrupt 0x0000 005C
7 14 settable EXTI1 EXTI Line1 interrupt 0x0000 005C
8 15 settable EXTI2 EXTI Line2 interrupt 0x0000 0060
9 16 settable EXTI3 EXTI Line3 interrupt 0x0000 0064
10 17 settable EXTI4 EXTI Line4 interrupt 0x0000 0068
11 18 settable DMA1_CH1 DMA1 channel 1 interrupt 0x0000 006C
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