Nested vectored interrupt controller (NVIC) RM0351
394/1830 DocID024597 Rev 5
12 19 settable DMA1_CH2 DMA1 channel 2 interrupt 0x0000 0070
13 20 settable DMA1_CH3 DMA1 channel 3 interrupt 0x0000 0074
14 21 settable DMA1_CH4 DMA1 channel 4 interrupt 0x0000 0078
15 22 settable DMA1_CH5 DMA1 channel 5 interrupt 0x0000 007C
16 23 settable DMA1_CH6 DMA1 channel 6 interrupt 0x0000 0080
17 24 settable DMA1_CH7 DMA1 channel 7 interrupt 0x0000 0084
18 25 settable ADC1_2 ADC1 and ADC2 global interrupt 0x0000 0088
19 26 settable CAN1_TX CAN1_TX interrupts 0x0000 008C
20 27 settable CAN1_RX0 CAN1_RX0 interrupts 0x0000 0090
21 28 settable CAN1_RX1 CAN1_RX1 interrupt 0x0000 0094
22 29 settable CAN1_SCE CAN1_SCE interrupt 0x0000 0098
23 30 settable EXTI9_5 EXTI Line[9:5] interrupts 0x0000 009C
24 31 settable TIM1_BRK/TIM15 TIM1 Break/TIM15 global interrupts 0x0000 00A0
25 32 settable TIM1_UP/TIM16 TIM1 Update/TIM16 global interrupts 0x0000 00A4
26 33 settable
TIM1_TRG_COM
/TIM17
TIM1 trigger and commutation/TIM17
interrupts
0x0000 00A8
27 34 settable TIM1_CC TIM1 capture compare interrupt 0x0000 00AC
28 35 settable TIM2 TIM2 global interrupt 0x0000 00B0
29 36 settable TIM3 TIM3 global interrupt 0x0000 00B4
30 37 settable TIM4 TIM4 global interrupt 0x0000 00B8
31 38 settable I2C1_EV I2C1 event interrupt 0x0000 00BC
32 39 settable I2C1_ER I2C1 error interrupt 0x0000 00C0
33 40 settable I2C2_EV I2C2 event interrupt 0x0000 00C4
34 41 settable I2C2_ER I2C2 error interrupt 0x0000 00C8
35 42 settable SPI1 SPI1 global interrupt 0x0000 00CC
36 43 settable SPI2 SPI2 global interrupt 0x0000 00D0
37 44 settable USART1 USART1 global interrupt 0x0000 00D4
38 45 settable USART2 USART2 global interrupt 0x0000 00D8
39 46 settable USART3 USART3 global interrupt 0x0000 00DC
40 47 settable EXTI15_10 EXTI Line[15:10] interrupts 0x0000 00E0
41 48 settable RTC_ALARM RTC alarms through EXTI line 18 interrupts 0x0000 00E4
42 49 settable DFSDM1_FLT3 DFSDM1_FLT3 global interrupt 0x0000 00E8
43 50 settable TIM8_BRK TIM8 Break interrupt 0x0000 00EC
Table 57. STM32L4x5/STM32L4x6 vector table (continued)
Position
Priority
Type of
priority
Acronym Description Address
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