Analog-to-digital converters (ADC) RM0351
556/1830 DocID024597 Rev 5
Analog watchdog
The analog watchdog functionality is maintained (AWDSGL and AWDEN bits), with the
following difference:
– the RES[1:0] bits are ignored, comparison is always done on using the full 12-bit
values HT[11:0] and LT[11:0]
– the comparison is performed on the most significant 12-bit of the 16-bit
oversampled results ADC_DR[15:4]
Note: Care must be taken when using high shifting values, this will reduce the comparison range.
For instance, if the oversampled result is shifted by 4 bits, thus yielding a 12-bit data right-
aligned, the effective analog watchdog comparison can only be performed on 8 bits. The
comparison is done between ADC_DR[11:4] and HT[0:7] / LT[[0:7], and HT[11:8] / LT[11:8]
must be kept reset.
Triggered mode
The averager can also be used for basic filtering purpose. Although not a very powerful filter
(slow roll-off and limited stop band attenuation), it can be used as a notch filter to reject
constant parasitic frequencies (typically coming from the mains or from a switched mode
power supply). For this purpose, a specific discontinuous mode can be enabled with
TROVS bit in ADC_CFGR2, to be able to have an oversampling frequency defined by a
user and independent from the conversion time itself.
The Figure 113 below shows how conversions are started in response to triggers during
discontinuous mode.
If the TROVS bit is set, the content of the DISCEN bit is ignored and considered as 1.
Figure 113. Triggered regular oversampling mode (TROVS bit = 1)
Injected and regular sequencer management when oversampling
In oversampling mode, it is possible to have differentiated behavior for injected and regular
sequencers. The oversampling can be enabled for both sequencers with some limitations if
they have to be used simultaneously (this is related to a unique accumulation unit).
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