Digital filter for sigma delta modulators (DFSDM) RM0351
728/1830 DocID024597 Rev 5
• Analog watchdog interrupt:
– occurred when converted data (output data or data from analog watchdog filter -
according to AWFSEL bit setting in DFSDM_FLTxCR1 register) crosses
over/under high/low thresholds in DFSDM_FLTxAWHTR / DFSDM_FLTxAWLTR
registers
– enabled by AWDIE bit in DFSDM_FLTxCR2 register (on selected channels
AWDCH[7:0])
– indicated in AWDF bit in DFSDM_FLTxISR register
– separate indication of high or low analog watchdog threshold error by AWHTF[7:0]
and AWLTF[7:0] fields in DFSDM_FLTxAWSR register
– cleared by writing ‘1’ into corresponding CLRAWHTF[7:0] or CLRAWLTF[7:0] bits
in DFSDM_FLTxAWCFR register
• Short-circuit detector interrupt:
– occurred when the number of stable data crosses over thresholds in
DFSDM_CHyAWSCDR register
– enabled by SCDIE bit in DFSDM_FLTxCR2 register (on channel selected by
SCDEN bi tin DFSDM_CHyCFGR1 register)
– indicated in SCDF[7:0] bits in DFSDM_FLTxISR register (which also reports the
channel on which the short-circuit detector event occurred)
– cleared by writing ‘1’ into the corresponding CLRSCDF[7:0] bit in
DFSDM_FLTxICR register
• Channel clock absence interrupt:
– occurred when there is clock absence on CKINy pin (see Clock absence detection
in Section 24.4.4: Serial channel transceivers)
– enabled by CKABIE bit in DFSDM_FLTxCR2 register (on channels selected by
CKABEN bit in DFSDM_CHyCFGR1 register)
– indicated in CKABF[y] bit in DFSDM_FLTxISR register
– cleared by writing ‘1’ into CLRCKABF[y] bit in DFSDM_FLTxICR register
Table 158. DFSDM interrupt requests
Interrupt event Event flag
Event/Interrupt clearing
method
Interrupt enable
control bit
End of injected conversion JEOCF reading DFSDM_FLTxJDATAR JEOCIE
End of regular conversion REOCF reading DFSDM_FLTxRDATAR REOCIE
Injected data overrun JOVRF writing CLRJOVRF = 1 JOVRIE
Regular data overrun ROVRF writing CLRROVRF = 1 ROVRIE
Analog watchdog
AWDF,
AWHTF[7:0],
AWLTF[7:0]
writing CLRAWHTF[7:0] = 1
writing CLRAWLTF[7:0] = 1
AWDIE,
(AWDCH[7:0])
short-circuit detector SCDF[7:0] writing CLRSCDF[7:0] = 1
SCDIE,
(SCDEN)
Channel clock absence CKABF[7:0] writing CLRCKABF[7:0] = 1
CKABIE,
(CKABEN)
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