DocID024597 Rev 5 727/1830
RM0351 Digital filter for sigma delta modulators (DFSDM)
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the sequence of injected conversions finishes, the continuous regular conversions start
again if RCONT is still set (and RPEND bit will signalize the delayed start on the first regular
conversion result).
Precedence also matters when actions are initiated by the same write to DFSDM, or if
multiple actions are pending at the end of another action. For example, suppose that, while
an injected conversion is in process (JCIP=1), a single write operation to DFSDM_FLTxCR1
writes ‘1’ to RSWSTART, requesting a regular conversion. When the injected sequence
finishes, the precedence dictates that the regular conversion is performed next and its
delayed start is signalized in RPEND bit.
24.4.18 Power optimization in run mode
In order to reduce the consumption, the DFSDM filter and integrator are automatically put
into idle when not used by conversions (RCIP=0, JCIP=0).
24.5 DFSDM interrupts
In order to increase the CPU performance, a set of interrupts related to the CPU event
occurrence has been implemented:
• End of injected conversion interrupt:
– enabled by JEOCIE bit in DFSDM_FLTxCR2 register
– indicated in JEOCF bit in DFSDM_FLTxISR register
– cleared by reading DFSDM_FLTxJDATAR register (injected data)
– indication of which channel end of conversion occurred, reported in JDATACH[2:0]
bits in DFSDM_FLTxJDATAR register
• End of regular conversion interrupt:
– enabled by REOCIE bit in DFSDM_FLTxCR2 register
– indicated in REOCF bit in DFSDM_FLTxISR register
– cleared by reading DFSDM_FLTxRDATAR register (regular data)
– indication of which channel end of conversion occurred, reported in
RDATACH[2:0] bits in DFSDM_FLTxRDATAR register
(a)
• Data overrun interrupt for injected conversions:
– occurred when injected converted data were not read from DFSDM_FLTxJDATAR
register (by CPU or DMA) and were overwritten by a new injected conversion
– enabled by JOVRIE bit in DFSDM_FLTxCR2 register
– indicated in JOVRF bit in DFSDM_FLTxISR register
– cleared by writing ‘1’ into CLRJOVRF bit in DFSDM_FLTxICR register
• Data overrun interrupt for regular conversions:
– occurred when regular converted data were not read from DFSDM_FLTxRDATAR
register (by CPU or DMA) and were overwritten by a new regular conversion
– enabled by ROVRIE bit in DFSDM_FLTxCR2 register
– indicated in ROVRF bit in DFSDM_FLTxISR register
– cleared by writing ‘1’ into CLRROVRF bit in DFSDM_FLTxICR register
a. Available only for STM32L496xx/4A6xx devices.
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