DocID024597 Rev 5 1775/1830
RM0351 Debug support (DBG)
1807
48 Debug support (DBG)
48.1 Overview
The STM32L4x5/STM32L4x6 devices are built around a Cortex
®
-M4 core which contains
hardware extensions for advanced debugging features. The debug extensions allow the
core to be stopped either on a given instruction fetch (breakpoint) or data access
(watchpoint). When stopped, the core’s internal state and the system’s external state may
be examined. Once examination is complete, the core and the system may be restored and
program execution resumed.
The debug features are used by the debugger host when connecting to and debugging the
STM32L4x5/STM32L4x6 MCUs.
Two interfaces for debug are available:
• Serial wire
• JTAG debug port
Figure 542. Block diagram of STM32 MCU and Cortex
®
-M4-level debug support
Note: The debug features embedded in the Cortex
®
-M4 core are a subset of the ARM
®
CoreSight
Design Kit.
#ORTEX-
#ORE
37*$0
!("!0
"RIDGE
.6)#
$74
&0"
)4-
%4-
$#ODE
INTERFACE
3YSTEM
INTERFACE
)NTERNALPRIVATE
PERIPHERALBUS00"
%XTERNALPRIVATE
PERIPHERALBUS00"
"USMATRIX
$ATA
4RACEPORT
$"'-#5
34--#5DEBUGSUPPORT
#ORTEX-DEBUGSUPPORT
*4-3
*4$)
*4$/
.*4234
*4#+
37$)/
37#,+
42!#%37/
42!#%37/
42!#%#+
42!#%$;=
40)5
-36
To Next Page
Loading...
Need help?
General
