DocID024597 Rev 5 435/1830
RM0351 Flexible static memory controller (FSMC)
471
Note: The FMC_BWTRx register is valid only if the extended mode is set (mode B), otherwise its
content is don’t care.
Mode C - NOR Flash - OE toggling
Figure 45. ModeC read access waveforms
Table 79. FMC_BWTRx bit fields
Bit number Bit name Value to set
31:30 Reserved 0x0
29:28 ACCMOD 0x1 if extended mode is set
27:24 DATLAT Don’t care
23:20 CLKDIV Don’t care
19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
15:8 DATAST
Duration of the access second phase (DATAST HCLK cycles) for
write accesses.
7:4 ADDHLD Don’t care
3:0 ADDSET
Duration of the access first phase (ADDSET HCLK cycles) for write
accesses. Minimum value for ADDSET is 0.
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