Nested vectored interrupt controller (NVIC) RM0351
392/1830 DocID024597 Rev 5
13 Nested vectored interrupt controller (NVIC)
13.1 NVIC main features
• 82 (for STM32L475xx/476xx/486xx devices), 91 (for STM32L496xx/4A6xx devices)
maskable interrupt channels (not including the sixteen Cortex
®
-M4 with FPU interrupt
lines)
• 16 programmable priority levels (4 bits of interrupt priority are used)
• Low-latency exception and interrupt handling
• Power management control
• Implementation of System Control Registers
The NVIC and the processor core interface are closely coupled, which enables low latency
interrupt processing and efficient processing of late arriving interrupts.
All interrupts including the core exceptions are managed by the NVIC. For more information
on exceptions and NVIC programming, refer to the PM0214 programming manual for
Cortex
TM
-M4 products.
13.2 SysTick calibration value register
The SysTick calibration value is set to 0x0000270F, which gives a reference time base of
1 ms with the SysTick clock set to 10 MHz (max f
HCLK
/8).
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