DocID024597 Rev 5 367/1830
RM0351 Chrom-Art Accelerator™ controller (DMA2D)
391
to obtain a fully opaque pixel. The alpha value can be modified according to the AM[1:0] bits
of the DMA2D_FGPFCCR register:
• It can be unchanged.
• It can be replaced by the value defined in the ALPHA[7:0] value of the
DMA2D_FGPFCCR register.
• It can be replaced by the original value multiplied by the ALPHA[7:0] value of the
DMA2D_FGPFCCR register divided by 255.
The resulting 32-bit data are encoded by the OUT PFC into the format specified by the
CM[2:0] field of the DMA2D_OPFCCR register. The output pixel format cannot be the
indirect mode since no CLUT generation process is supported.
The processed data are written into the destination memory location pointed by
DMA2D_OMAR.
Memory-to-memory with PFC and blending
In this mode, 2 sources are fetched in the foreground FIFO and background FIFO from the
memory locations defined by DMA2D_FGMAR and DMA2D_BGMAR.
The two pixel format converters have to be configured as described in the memory-to-
memory mode. Their configurations can be different as each pixel format converter are
independent and have their own CLUT memory.
Once each pixel has been converted into 32 bits by their respective PFCs, they are blended
according to the equation below:
The resulting 32-bit pixel value is encoded by the output PFC according to the specified
output format, and the data are written into the destination memory location pointed by
DMA2D_OMAR.
Configuration error detection
The DMA2D checks that the configuration is correct before any transfer. The configuration
error interrupt flag is set by hardware when a wrong configuration is detected when a new
transfer/automatic loading starts. An interrupt is then generated if the CEIE bit of the
DMA2D_CR is set.
C
OUT
=
with α
Mult
=
C
FG
.α
FG
+ C
BG
.α
BG
- C
BG
.α
Mult
α
OUT
255
α
FG
. α
BG
with C = R or G or B
α
OUT
= α
FG
+ α
BG
- α
Mult
Division are rounded to the nearest lower integer
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