ST STM32L4 5 Series User Manual

DocID024597 Rev 5 365/1830
RM0351 Chrom-Art Accelerator™ controller (DMA2D)
391
The RGB888 aligned on 32-bit is supported through the ARGB8888 mode.
12.3.9 DMA2D AHB master port timer
An 8-bit timer is embedded into the AHB master port to provide an optional limitation of the
bandwidth on the crossbar.
This timer is clocked by the AHB clock and counts a dead time between two consecutive
accesses. This limits the bandwidth usage.
The timer enabling and the dead time value are configured through the AHB master port
timer configuration register (DMA2D_AMPTCR).
12.3.10 DMA2D transactions
DMA2D transactions consist of a sequence of a given number of data transfers. The
number of data and the width can be programmed by software.
Each DMA2D data transfer is composed of up to 4 steps:
1. Data loading from the memory location pointed by the DMA2D_FGMAR register and
pixel format conversion as defined in DMA2D_FGCR.
2. Data loading from a memory location pointed by the DMA2D_BGMAR register and
pixel format conversion as defined in DMA2D_BGCR.
3. Blending of all retrieved pixels according to the alpha channels resulting of the PFC
operation on alpha values.
4. Pixel format conversion of the resulting pixels according to the DMA2D_OCR register
and programming of the data to the memory location addressed through the
DMA2D_OMAR register.
12.3.11 DMA2D configuration
Both source and destination data transfers can target peripherals and memories in the
whole 4 Gbyte memory area, at addresses ranging between 0x0000 0000 and
0xFFFF FFFF.
The DMA2D can operate in any of the four following modes selected through MODE[1:0]
bits of the DMA2D_CR register:
• Register-to-memory
• Memory-to-memory
• Memory-to-memory with PFC
• Memory-to-memory with PFC and blending
Register-to-memory
The register-to-memory mode is used to fill a user defined area with a predefined color.
ARGB1555 A
1
[0]R
1
[4:0]G
1
[4:3] G
1
[2:0]B
1
[4:0] A
0
[0]R
0
[4:0]G
0
[4:3] G
0
[2:0]B
0
[4:0]
ARGB4444 A
1
[3:0]R
1
[3:0] G
1
[3:0]B
1
[3:0] A
0
[3:0]R
0
[3:0] G
0
[3:0]B
0
[3:0]
Table 54. Data order in memory (continued)
Color Mode@ + 3@ + 2@ + 1@ + 0

ST STM32L4 5 Series Specifications

General

Brand	ST
Model	STM32L4 5 Series
Category	Microcontrollers
Language	English