ST STM32L4 5 Series - Page 1812

Revision history RM0351
1812/1830 DocID024597 Rev 5
15-Oct-2015
2
(continued)
I2C
Updated Section 39.4.4: I2C initialization, including
Figure 374: Setup and hold timings.
Updated Section 39.7.5: Timing register
(I2C_TIMINGR).
SPI
Updated Figure 441, Figure 442, Figure 443 and
Figure 444.
Notes updated and added below Figure 441,
Figure 442, Figure 443.
Added Section 42.4.4: Multi-master communication.
UART
Updated Note:.
Added Section : Determining the maximum USART
baudrate allowing to wakeup correctly from Stop mode
when the USART clock source is the HSI clock.
Removed TXFRQ bit in Table 241: LPUART register
map and reset values.
DEBUG
Updated Section : DBGMCU_IDCODE.
08-Dec-2015 3
In all the document:
– Stop 1 with main regulator becomes Stop 0
– Stop 1 with low-power regulator remains as Stop 1
MEM
Updated SAI1 and SAI2 base address in Table 2: C at. 2
devices memory map and peripheral register boundary
addresses.
MMAP
Added Table 6: Memory mapping versus boot
mode/physical remap.
FLASH
Added Note: in Section : Fast programming.
PWR
Updated Table 24: Functionalities depending on the
working mode.
RCC
Updated WWDGEN bit description and access mode in
Section 6.4.19: APB1 peripheral clock enable register 1
(RCC_APB1ENR1).
NVIC
Updated Figure 33: External interrupt/event GPIO
mapping.
Updated reset value in Section 14.5.7: Interrupt mask
register 2 (EXTI_IMR2).
Table 327. Document revision history (continued)
Date Revision Changes