General-purpose timers (TIM15/TIM16/TIM17) RM0351
1108/1830 DocID024597 Rev 5
32.5.18 TIM15 option register 1 (TIM15_OR1)
Address offset: 0x50
Reset value: 0x0000
32.5.19 TIM15 option register 2 (TIM15_OR2)
Address offset: 0x60
Reset value: 0x0000 0001
Bits 15:0 DMAB[15:0]: DMA register for burst accesses
A read or write operation to the DMAR register accesses the register located at the address
(TIMx_CR1 address) + (DBA + DMA index) x 4
where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base
address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA
transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).
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1514131211109876543210
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ENCODER_
MODE[1:0]
TI1_
RMP
rw rw rw
Bits 31:3 Reserved, must be kept at reset value.
Bits 2:1 ENCODER_MODE[1:0]: Encoder mode
00: No redirection
01:TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
10:TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
11:TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
Bit 0 TI1_RMP: Input capture 1 remap
0: TIM15 input capture 1 is connected to I/O
1: TIM15 input capture 1 is connected to LSE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res
1514131211109876543210
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BKCM
P2P
BKCM
P1P
BKINP
BKDF1
BK0E
Res Res Res. Res. Res.
BKCM
P2E
BKCM
P1E
BKINE
rw rw rw rw rw rw rw
Bits 31:12 Reserved, must be kept at reset value.
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