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ST STM32L4 5 Series - Page 1610

ST STM32L4 5 Series
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Controller area network (bxCAN) RM0351
1610/1830 DocID024597 Rev 5
CAN receive FIFO mailbox data length control and time stamp register
(CAN_RDTxR) (x = 0..1)
Address offsets: 0x1B4, 0x1C4
Reset value: 0xXXXX XXXX
All RX registers are write protected.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIME[15:0]
rrrrrrrrrrrrrrrr
1514131211109876543210
FMI[7:0] Res. Res. Res. Res. DLC[3:0]
rrrrrrrr rrrr
Bits 31:16 TIME[15:0]: Message time stamp
This field contains the 16-bit timer value captured at the SOF detection.
Bits 15:8 FMI[7:0]: Filter match index
This register contains the index of the filter the message stored in the mailbox passed
through. For more details on identifier filtering refer to Section 46.7.4: Identifier filtering on
page 1585 - Filter Match Index paragraph.
Bits 7:4 Reserved, must be kept at reset value.
Bits 3:0 DLC[3:0]
: Data length code
This field defines the number of data bytes a data frame contains (0 to 8). It is 0 in the case
of a remote frame request.

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