ST STM32L4 5 Series User Manual

USB on-the-go full-speed (OTG_FS) RM0351
1664/1830 DocID024597 Rev 5
47.15.7 OTG interrupt mask register (OTG_GINTMSK)
Address offset: 0x018
Reset value: 0x0000 0000
This register works with the Core interrupt register to interrupt the application. When an
interrupt bit is masked, the interrupt associated with that bit is not generated. However, the
Core Interrupt (OTG_GINTSTS) register bit corresponding to that interrupt is still set.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUIM SRQIM
DISCIN
T
CIDSC
HGM
LPMIN
TM
PTXFE
M
HCIM PRTIM
RSTDE
TM
Res.
IPXFR
M/IISO
OXFR
M
IISOIX
FRM
OEPIN
T
IEPINT Res. Res.
rw rw rw rw
rw
rw rw r
rw
rw rw rw rw
1514131211109876543210
EOPF
M
ISOOD
RPM
ENUM
DNEM
USBRS
T
USBSU
SPM
ESUSP
M
Res. Res.
GONA
KEFFM
GINAK
EFFM
NPTXF
EM
RXFLV
LM
SOFM
OTGIN
T
MMISM Res.
rw rw rw rw rw rw rw rw rw rw rw rw rw
Bit 31 WUIM: Resume/remote wakeup detected interrupt mask
0: Masked interrupt
1: Unmasked interrupt
Note: Accessible in both host and device modes.
Bit 30 SRQIM: Session request/new session detected interrupt mask
0: Masked interrupt
1: Unmasked interrupt
Note: Accessible in both host and device modes.
Bit 29 DISCINT: Disconnect detected interrupt mask
0: Masked interrupt
1: Unmasked interrupt
Note: Only accessible in device mode.
Bit 28 CIDSCHGM: Connector ID status change mask
0: Masked interrupt
1: Unmasked interrupt
Note: Accessible in both host and device modes.
Bit 27 LPMINTM: LPM interrupt mask
0: Masked interrupt
1: Unmasked interrupt
Note: Accessible in both host and device modes.
Bit 26 PTXFEM: Periodic Tx FIFO empty mask
0: Masked interrupt
1: Unmasked interrupt
Note: Only accessible in host mode.
Bit 25 HCIM: Host channels interrupt mask
0: Masked interrupt
1: Unmasked interrupt
Note: Only accessible in host mode.

ST STM32L4 5 Series Specifications

General

Brand	ST
Model	STM32L4 5 Series
Category	Microcontrollers
Language	English