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ST STM32L4 5 Series User Manual

ST STM32L4 5 Series
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Reset and clock control (RCC) RM0351
232/1830 DocID024597 Rev 5
6.4.7 Clock interrupt enable register (RCC_CIER)
Address offset: 0x18
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
Bit 17 PLLSAI2P: SAI1PLL division factor for PLLSAI2CLK (SAI1 or SAI2 clock).
Set and cleared by software to control the frequency of the SAI2PLL output clock
PLLSAI2CLK. This output can be selected for SAI1 or SAI2. These bits can be written only if
SAI2PLL is disabled.
(when the PLLSAI2PDIV[4:0] is set to “00000” on STM32L496xx/4A6xx devices),
PLLSAI2CLK output clock frequency = VCOSAI2 frequency / PLLSAI2P with PLLSAI2P =7,
or 17
0: PLLSAI2P = 7
1: PLLSAI2P = 17
Bit 16 PLLSAI2PEN: SAI2PLL PLLSAI2CLK output enable
Set and reset by software to enable the PLLSAI2CLK output of the SAI2PLL.
In order to save power, when the PLLSAI2CLK output of the SAI2PLL is not used, the value
of PLLSAI2PEN should be 0.
0: PLLSAI2CLK output disable
1: PLLSAI2CLK output enable
Bit 15 Reserved, must be kept at reset value.
Bits 14:8 PLLSAI2N[6:0]: SAI2PLL multiplication factor for VCO
Set and cleared by software to control the multiplication factor of the VCO. These bits can be
written only when the SAI2PLL is disabled.
VCOSAI2 output frequency = VCOSAI2 input frequency x PLLSAI2N
with 8 =< PLLSAI2N =< 86
0000000: PLLSAI2N = 0 wrong configuration
0000001: PLLSAI2N = 1 wrong configuration
...
0000111: PLLSAI2N = 7 wrong configuration
0001000: PLLSAI2N = 8
0001001: PLLSAI2N = 9
...
1010101: PLLSAI2N = 85
1010110: PLLSAI2N = 86
1010111: PLLSAI2N = 87 wrong configuration
...
1111111: PLLSAI2N = 127 wrong configuration
Caution: The software has to set correctly these bits to ensure that the VCO
output frequency is between 64 and 344 MHz.
Bits 7:0 Reserved, must be kept at reset value.

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ST STM32L4 5 Series Specifications

General IconGeneral
BrandST
ModelSTM32L4 5 Series
CategoryMicrocontrollers
LanguageEnglish

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