ST STM32L4 5 Series User Manual

DocID024597 Rev 5 261/1830
RM0351 Reset and clock control (RCC)
278
Bit 20 UART5SMEN: UART5 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: UART5 clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: UART5 clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 19 UART4SMEN: UART4 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: UART4 clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: UART4 clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 18 USART3SMEN: USART3 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: USART3 clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: USART3 clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 17 USART2SMEN: USART2 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: USART2 clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: USART2 clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 16 Reserved, must be kept at reset value.
Bit 15 SPI3SMEN: SPI3 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SPI3 clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: SPI3 clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 14 SPI2SMEN: SPI2 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SPI2 clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: SPI2 clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WWDGSMEN: Window watchdog clocks enable during Sleep and Stop modes
Set and cleared by software. This bit is forced to ‘1’ by hardware when the hardware WWDG
option is activated.
0: Window watchdog clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: Window watchdog clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 10 RTCAPBSMEN: RTC APB clock enable during Sleep and Stop modes
(This bit is reserved for STM32L475xx/476xx/486xx devices)
Set and cleared by software
0: RTC APB clock disabled by the clock gating
(1)
during Sleep and Stop modes
1: RTC APB clock enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 9 LCDSMEN: LCD clocks enable during Sleep and Stop modes
Set and cleared by software.
0: LCD clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: LCD clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bits 8:6 Reserved, must be kept at reset value.
Bit 5 TIM7SMEN: TIM7 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: TIM7 clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: TIM7 clocks enabled by the clock gating
(1)
during Sleep and Stop modes

ST STM32L4 5 Series Specifications

General

Brand	ST
Model	STM32L4 5 Series
Category	Microcontrollers
Language	English