Reset and clock control (RCC) RM0351
266/1830 DocID024597 Rev 5
Bit 31 DFSDM1SEL: DFSDM1 clock source selection
This bit is set and cleared by software to select the DFSDM1 clock source.
0: APB2 (PCLK2) selected as DFSDM1 clock
1: System clock (SYSCLK) used as DFSDM1 clock
Bit 30 SWPMI1SEL: SWPMI1 clock source selection
This bit is set and cleared by software to select the SWPMI1 clock source.
0: APB1 (PCLK1) selected as SWPMI1 clock
1: HSI16 clock selected as SWPMI1 clock
Bits 29:28 ADCSEL[1:0]: ADCs clock source selection
These bits are set and cleared by software to select the clock source used by the ADC
interface.
00: No clock selected
01: PLLSAI1 “R” clock (PLLADC1CLK) selected as ADCs clock
10: PLLSAI2 “R” clock (PLLADC2CLK) selected as ADCs clock
11: System clock selected as ADCs clock
Bits 27:26 CLK48SEL[1:0]: 48 MHz clock source selection
These bits are set and cleared by software to select the 48 MHz clock source used by USB
OTG FS, RNG and SDMMC.
00: HSI48 clock selected as 48 MHz clock (only for STM32L496xx/4A6xx devices, otherwise
no clock selected)
01: PLLSAI1 “Q” clock (PLL48M2CLK) selected as 48 MHz clock
10: PLL “Q” clock (PLL48M1CLK) selected as 48 MHz clock
11: MSI clock selected as 48 MHz clock
Bits 25:24 SAI2SEL[1:0]: SAI2 clock source selection
These bits are set and cleared by software to select the SAI2 clock source.
00: PLLSAI1 “P” clock (PLLSAI1CLK) selected as SAI2 clock
01: PLLSAI2 “P” clock (PLLSAI2CLK) selected as SAI2 clock
10: PLL “P” clock (PLLSAI3CLK) selected as SAI2 clock
11: External input SAI2_EXTCLK selected as SAI2 clock
Caution: If the selected clock is the external clock, it is not possible to switch to
another clock if the external clock is not present.
Bits 23:22 SAI1SEL[1:0]: SAI1 clock source selection
These bits are set and cleared by software to select the SAI1 clock source.
00: PLLSAI1 “P” clock (PLLSAI1CLK) selected as SAI1 clock
01: PLLSAI2 “P” clock (PLLSAI2CLK) selected as SAI1 clock
10: PLL “P” clock (PLLSAI3CLK) selected as SAI1 clock
11: External input SAI1_EXTCLK selected as SAI1 clock
Caution: If the selected clock is the external clock, it is not possible to switch to
another clock if the external clock is not present.
Bits 21:20 LPTIM2SEL[1:0]: Low power timer 2 clock source selection
These bits are set and cleared by software to select the LPTIM2 clock source.
00: PCLK selected as LPTIM2 clock
01: LSI clock selected as LPTIM2 clock
10: HSI16 clock selected as LPTIM2 clock
11: LSE clock selected as LPTIM2 clock
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