DocID024597 Rev 5 321/1830
RM0351 System configuration controller (SYSCFG)
323
9.2.11 SYSCFG SRAM2 write protection register 2 (SYSCFG_SWPR2)
Address offset: 0x28
System reset value: 0x0000 0000
Only for STM32L496xx/4A6xx devices.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res
1514131211109876543210
Res Res Res Res Res Res Res Res KEY[7:0]
wwwwwwww
Bits 31:8 Reserved, must be kept at reset value
Bits 7:0 KEY[7:0]: SRAM2 write protection key for software erase
The following steps are required to unlock the write protection of the SRAM2ER
bit in the SYSCFG_CFGR2 register.
1. Write "0xCA” into Key[7:0]
2. Write "0x53” into Key[7:0]
Writing a wrong key reactivates the write protection.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P63WP P62WP P61WP P60WP P59WP P58WP P57WP P56WP P55WP P54WP P53WP P52WP P51WP P50WP P49WP P48WP
rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs
1514131211109876543210
P47WP P46WP P45WP P44WP P43WP P42WP P41WP P40WP P39WP P38WP P37WP P36WP P35WP P34WP P33WP P32WP
rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs
Bits 31:0 PxWP (x= 32 to 63): SRAM2 page x write protection
These bits are set by software and cleared only by a system reset.
0: Write protection of SRAM2 page x is disabled.
1: Write protection of SRAM2 page x is enabled.
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