Direct memory access controller (DMA) RM0351
340/1830 DocID024597 Rev 5
11.4.7 DMA request mapping
DMA controller
The hardware requests from the peripherals (TIM1/2/3/4/5/6/7/8/15/16/17, ADC1/2/3,
DAC1/2, SPI1/2/3, I2C1/2/3/4, SDMMC1, QUADSPI, SWPMI1, DFSDM1, SAI1/2, AES,
HASH, DCMI, USART1/2/3, UART4/5 and LPUART1) are mapped to the DMA1 or DMA2
channels (1 to 7) through the DMA1/2 channel selection register.
Refer to Figure 30: DMA1 request mapping and Figure 31: DMA2 request mapping.
The peripheral DMA requests can be independently activated/de-activated by programming
the DMA control bit in the registers of the corresponding peripheral.
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