Direct memory access controller (DMA) RM0351
352/1830 DocID024597 Rev 5
11.5.8 DMA2 channel selection register (DMA2_CSELR)
Address offset: 0xA8 (with respect to DMA2 base address)
Reset value: 0x0000 0000
This register is used to manage the mapping of DMA channels (see Figure 31).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. C7S [3:0] C6S [3:0] C5S [3:0]
rw rw rw rw rw rw rw rw rw rw rw rw
1514131211109876543210
C4S [3:0] C3S [3:0] C2S [3:0] C1S [3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:24 C7S[3:0]: DMA channel 7 selection
0000: Reserved
0001: Channel 7 mapped on SAI1_B
0010: Channel 7 mapped on USART1_RX
0011: Channel 7 mapped on QUADSPI
0100: Channel 7 mapped on LPUART1_RX
0101: Channel 7 mapped on I2C1_TX
0110: Channel 7 mapped on HASH_IN
0111: Channel 7 mapped on TIM8_CH2
others: Reserved
Bits 23:20 C6S[3:0]: DMA channel 6 selection
0000: Channel 6 mapped on DCMI
0001: Channel 6 mapped on SAI1_A
0010: Channel 6 mapped on USART1_TX
0011: Reserved
0100: Channel 6 mapped on LPUART1_TX
0101: Channel 6 mapped on I2C1_RX
0110: Reserved
0111: Channel 6 mapped on TIM8_CH1
others: Reserved
Bits 19:16 C5S[3:0]: DMA channel 5 selection
0000: Channel 5 mapped on ADC3
0001: Reserved
0010: Channel 5 mapped on UART4_RX
0011: Channel 5 mapped on TIM7_UP/DAC2
0100: Channel 5 mapped on DCMI
0101: Channel 5 mapped on TIM5_CH1
0110: Channel 5 mapped on AES_IN
0111: Channel 5 mapped on SDMMC1
others: Reserved
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