List of figures RM0351
60/1830 DocID024597 Rev 5
Figure 196. CTR mode encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825
Figure 197. CTR mode decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825
Figure 198. 32-bit counter + nonce organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826
Figure 199. 128-bit block construction according to the data type. . . . . . . . . . . . . . . . . . . . . . . . . . . . 832
Figure 200. 128-bit block construction according to the data type (continued) . . . . . . . . . . . . . . . . . . 833
Figure 201. Mode 1: encryption with 128-bit key length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834
Figure 202. Mode 2: key derivation with 128-bit key length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834
Figure 203. Mode 3: decryption with 128-bit key length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835
Figure 204. Mode 4: key derivation and decryption with 128-bit key length . . . . . . . . . . . . . . . . . . . . 836
Figure 205. DMA requests and data transfers during Input phase (AES_IN) . . . . . . . . . . . . . . . . . . . 837
Figure 206. DMA requests during Output phase (AES_OUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837
Figure 207. HASH block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854
Figure 208. Message data swapping feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856
Figure 209. HASH save/restore mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861
Figure 210. HASH interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863
Figure 211. Advanced-control timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877
Figure 212. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 879
Figure 213. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 879
Figure 214. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881
Figure 215. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881
Figure 216. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 882
Figure 217. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 882
Figure 218. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . . 883
Figure 219. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . . . . . 883
Figure 220. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 885
Figure 221. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 885
Figure 222. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886
Figure 223. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886
Figure 224. Counter timing diagram, update event when repetition counter is not used. . . . . . . . . . . 887
Figure 225. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . . . . . . . . . . . 888
Figure 226. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 889
Figure 227. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 889
Figure 228. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890
Figure 229. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . . . . . . . . . 890
Figure 230. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 891
Figure 231. Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . . 892
Figure 232. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893
Figure 233. TIM1 ETR input circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893
Figure 234. TIM8 ETR input circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894
Figure 235. Control circuit in normal mode, internal clock divided by 1. . . . . . . . . . . . . . . . . . . . . . . . 895
Figure 236. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 896
Figure 237. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 897
Figure 238. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 897
Figure 239. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 898
Figure 240. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 899
Figure 241. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900
Figure 242. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3) . . . . . . . . . . . . 900
Figure 243. Output stage of capture/compare channel (channel 4). . . . . . . . . . . . . . . . . . . . . . . . . . . 901
Figure 244. Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . . . . . . . . . . . . . . 901
Figure 245. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 903
Figure 246. Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 905
Figure 247. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906
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