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Digital camera interface (DCMI) RM0351

662/1830 DocID024597 Rev 5

20.7.2 DCMI status register (DCMI_SR)

Address offset: 0x04

Reset value: 0x0000 0x0000

313029282726252423222120191817161514131211109876543210

Res.

FNE

VSYNC

HSYNC

rrr

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 FNE: FIFO not empty

This bit gives the status of the FIFO

1: FIFO contains valid data

0: FIFO empty

Bit 1 VSYNC

This bit gives the state of the DCMI_VSYNC pin with the correct programmed

polarity.

When embedded synchronization codes are used, the meaning of this bit is the

following:

0: active frame

1: synchronization between frames

In case of embedded synchronization, this bit is meaningful only if the

CAPTURE bit in DCMI_CR is set.

Bit 0 HSYNC

This bit gives the state of the DCMI_HSYNC pin with the correct programmed

polarity.

When embedded synchronization codes are used, the meaning of this bit is the

following:

0: active line

1: synchronization between lines

In case of embedded synchronization, this bit is meaningful only if the

CAPTURE bit in DCMI_CR is set.

ST STM32L4 5 Series User Manual

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