DocID024597 Rev 5 695/1830
RM0351 Operational amplifiers (OPAMP)
699
23.5 OPAMP registers
23.5.1 OPAMP1 control/status register (OPAMP1_CSR)
Address offset: 0x00
Reset value: 0x0000 0000
Standby
The OPAMP registers are powered down and must be re-initialized after
exiting Standby or Shutdown mode.
Shutdown
Table 149. Effect of low-power modes on the OPAMP
Mode Description
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OPA_
RANGE
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
rw
1514131211109876543210
CAL
OUT
USER
TRIM
CAL
SEL
CALON Res.
VP_
SEL
VM_SEL Res. Res. PGA_GAIN OPAMODE
OPA
LPM
OPAEN
r rwrwrw rwrwrw rwrwrw w rwrw
Bit 31 OPA_RANGE: Operational amplifier power supply range for stability
All AOP must be in power down to allow AOP-RANGE bit write. It applies to all AOP
embedded in the product.
0: Low range (VDDA < 2.4V)
1: High range (VDDA > 2.4V)
Bits 30:16 Reserved, must be kept at reset value.
Bit 15 CALOUT: Operational amplifier calibration output
During calibration mode offset is trimmed when this signal toggle.
Bit 14 USERTRIM: allows to switch from ‘factory’ AOP offset trimmed values to AOP offset ‘user’
trimmed values
This bit is active for both mode normal and low-power.
0: ‘factory’ trim code used
1: ‘user’ trim code used
Bit 13 CALSEL: Calibration selection
0: NMOS calibration (200mV applied on OPAMP inputs)
1: PMOS calibration (VDDA-200mV applied on OPAMP inputs)
Bit 12 CALON: Calibration mode enabled
0: Normal mode
1: Calibration mode (all switches opened by HW)
Bit 11 Reserved, must be kept at reset value.
Bit 10 VP_SEL: Non inverted input selection
0: GPIO connected to VINP
1: DAC connected to VINP
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