ST STM32L4 5 Series - Page 718

Digital filter for sigma delta modulators (DFSDM) RM0351
718/1830 DocID024597 Rev 5
Injected conversions can be launched by software or by a trigger. They are never
interrupted by regular conversions.
The regular channel is a selection of just one of the 8 channels. RCH[2:0] in the
DFSDM_FLTxCR1 register indicates the selected channel.
Regular conversions can be launched only by software (not by a trigger). A sequence of
continuous regular conversions is temporarily interrupted when an injected conversion is
requested.
Performing a conversion on a disabled channel (CHEN=0 in DFSDM_CHyCFGR1 register)
causes that the conversion will never end - because no input data is provided (with no clock
signal). In this case, it is necessary to enable a given channel (CHEN=1 in
DFSDM_CHyCFGR1 register) or to stop the conversion by DFEN=0 in DFSDM_FLTxCR1
register.
24.4.8 Digital filter configuration
DFSDM contains a Sinc
x
type digital filter implementation. This Sinc
x
filter performs an input
digital data stream filtering, which results in decreasing the output data rate (decimation)
and increasing the output data resolution. The Sinc
x
digital filter is configurable in order to
reach the required output data rates and required output data resolution. The configurable
parameters are:
• Filter order/type: (see FORD[2:0] bits in DFSDM_FLTxFCR register):
–FastSinc
–Sinc
1
–Sinc
2
–Sinc
3
–Sinc
4
–Sinc
5
• Filter oversampling/decimation ratio (see FOSR[9:0] bits in DFSDM_FLTxFCR
register):
– FOSR = 1-1024 - for FastSinc filter and Sinc
x
filter x = F
ORD
= 1..3
– FOSR = 1-215 - for Sinc
x
filter x = F
ORD
= 4
– FOSR = 1-73 - for Sinc
x
filter x = F
ORD
= 5
The filter has the following transfer function (impulse response in H domain):
• Sinc
x
filter type:
• FastSinc filter type:
Hz()
1z
FOSR–
–
1z
1–
–
---------------------------- -
⎝⎠
⎜⎟
⎛⎞
x
=
Hz()
1z
FOSR–
–
1z
1–
–
---------------------------- -
⎝⎠
⎜⎟
⎛⎞
2
1z
2FOSR⋅()–
+()⋅=