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ST STM32L4 5 Series User Manual

ST STM32L4 5 Series
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Digital filter for sigma delta modulators (DFSDM) RM0351
736/1830 DocID024597 Rev 5
Bit 17 RSWSTART: Software start of a conversion on the regular channel
0: Writing ‘0’ has no effect
1: Writing ‘1’ makes a request to start a conversion on the regular channel and causes RCIP to
become ‘1’. If RCIP=1 already, writing to RSWSTART has no effect. Writing ‘1’ has no effect if
RSYNC=1.
This bit is always read as ‘0’.
Bits 16:15 Reserved, must be kept at reset value.
Bits 14:13 JEXTEN[1:0]: Trigger enable and trigger edge selection for injected conversions
00: Trigger detection is disabled
01: Each rising edge on the selected trigger makes a request to launch an injected conversion
10: Each falling edge on the selected trigger makes a request to launch an injected conversion
11: Both rising edges and falling edges on the selected trigger make requests to launch injected
conversions
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Bits 12:11 Reserved, must be kept at reset value.
Bits 10:8 JEXTSEL[2:0]: Trigger signal selection for launching injected conversions
0x0-0x7: Trigger inputs selected by the following table.
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
DFSDM_FLT0 DFSDM_FLT1 DFSDM_FLT2 DFSDM_FLT3
0x00 dfsdm_jtrg0 dfsdm_jtrg0 dfsdm_jtrg0 dfsdm_jtrg0
0x01 dfsdm_jtrg1 dfsdm_jtrg1 dfsdm_jtrg1 dfsdm_jtrg1
0x02 dfsdm_jtrg2 dfsdm_jtrg2 dfsdm_jtrg2 dfsdm_jtrg2
0x03 dfsdm_jtrg3 dfsdm_jtrg3 dfsdm_jtrg3 dfsdm_jtrg4
0x04 dfsdm_jtrg5 dfsdm_jtrg5 dfsdm_jtrg5 dfsdm_jtrg6
0x05 dfsdm_jtrg7 dfsdm_jtrg7 dfsdm_jtrg8 dfsdm_jtrg8
0x06 dfsdm_jtrg9 dfsdm_jtrg9 dfsdm_jtrg9 dfsdm_jtrg9
0x07 dfsdm_jtrg10 dfsdm_jtrg10 dfsdm_jtrg10 dfsdm_jtrg10
Refer to Table 154: DFSDM triggers connection.
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 JDMAEN: DMA channel enabled to read data for the injected channel group
0: The DMA channel is not enabled to read injected data
1: The DMA channel is enabled to read injected data
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Bit 4 JSCAN: Scanning conversion mode for injected conversions
0: One channel conversion is performed from the injected channel group and next the selected
channel from this group is selected.
1: The series of conversions for the injected group channels is executed, starting over with the
lowest selected channel.
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel.
Bit 3 JSYNC: Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger
0: Do not launch an injected conversion synchronously with DFSDM_FLT0
1: Launch an injected conversion in this DFSDM_FLTx at the very moment when an injected
conversion is launched in DFSDM_FLT0 by its JSWSTART trigger
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).

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ST STM32L4 5 Series Specifications

General IconGeneral
BrandST
ModelSTM32L4 5 Series
CategoryMicrocontrollers
LanguageEnglish

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