Digital filter for sigma delta modulators (DFSDM) RM0351
742/1830 DocID024597 Rev 5
24.8.7 DFSDM data register for injected group (DFSDM_FLTxJDATAR)
Address offset: 0x118 + 0x80 * x, x = 0...3
Reset value: 0x0000 0000
Bits 31:29 FORD[2:0]: Sinc filter order
0: FastSinc filter type
1: Sinc
1
filter type
2: Sinc
2
filter type
3: Sinc
3
filter type
4: Sinc
4
filter type
5: Sinc
5
filter type
6-7: Reserved
Sinc
x
filter type transfer function:
FastSinc filter type transfer function:
This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1).
Bits 28:26 Reserved, must be kept at reset value.
Bits 25:16 FOSR[9:0]: Sinc filter oversampling ratio (decimation rate)
0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (F
OSR
= FOSR[9:0] +1). This
number is also the decimation ratio of the output data rate from filter.
This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1)
Note: If FOSR = 0, then the filter has no effect (filter bypass).
Bits 15:8 Reserved, must be kept at reset value.
Bits 7:0 IOSR[7:0]: Integrator oversampling ratio (averaging length)
0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples
from Sinc filter will be summed into one output data sample from the integrator. The output data rate
from the integrator will be decreased by this number (additional data decimation ratio).
This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1)
Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass).
Hz()
1z
FOSR–
–
1z
1–
–
---------------------------- -
⎝⎠
⎜⎟
⎛⎞
x
=
Hz()
1z
FOSR–
–
1z
1–
–
---------------------------- -
⎝⎠
⎜⎟
⎛⎞
2
1z
2FOSR⋅()–
+()⋅=
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA[23:8]
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1514131211109876543210
JDATA[7:0] Res. Res. Res. Res. Res. JDATACH[2:0]
rrrrrrrr rrr
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