DocID024597 Rev 5 745/1830
RM0351 Digital filter for sigma delta modulators (DFSDM)
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24.8.11 DFSDM analog watchdog status register (DFSDM_FLTxAWSR)
Address offset: 0x128 + 0x80 * x, x = 0...3
Reset value: 0x0000 0000
Note: All the bits of DFSDM_FLTxAWSR are automatically reset when DFEN=0.
24.8.12 DFSDM analog watchdog clear flag register
(DFSDM_FLTxAWCFR)
Address offset: 0x12C + 0x80 * x, x = 0...3
Reset value: 0x0000 0000
Bits 31:8 AWLT[23:0]: Analog watchdog low threshold
These bits are written by software to define the low threshold for the analog watchdog.
Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define
the 16-bit threshold as compared with the analog watchdog filter output (because data coming
from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into
comparison in this case.
Bits 7:4 Reserved, must be kept at reset value.
Bits 3:0 BKAWL[3:0]: Break signal assignment to analog watchdog low threshold event
BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event
BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
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AWHTF[7:0] AWLTF[7:0]
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Bits 31:16 Reserved, must be kept at reset value.
Bits 15:8 AWHTF[7:0]: Analog watchdog high threshold flag
AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by
software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register.
Bits 7:0 AWLTF[7:0]: Analog watchdog low threshold flag
AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by
software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
CLRAWHTF[7:0] CLRAWLTF[7:0]
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