Advanced encryption standard hardware accelerator (AES) RM0351
848/1830 DocID024597 Rev 5
28.14.11 AES initialization vector register 2 (AES_IVR2) (IVR[95:64])
Address offset: 0x28
Reset value: 0x0000 0000
28.14.12 AES initialization vector register 3 (AES_IVR3) (MSB: IVR[127:96])
Address offset: 0x2C
Reset value: 0x0000 0000
28.14.13 AES key register 4 (AES_KEYR4) (key[159:128])
Address offset: 0x30
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IVR2[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IVR2[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:0 IVR2[31:0]: Initialization vector register (IVR[95:64])
This register must be written before the EN bit in the AES_CR register is set:
The register value has no meaning if:
– The ECB mode (electronic codebook) is selected.
– The CTR or CBC mode is selected in addition with the key derivation or key derivation + decryption
mode.
In CTR mode (counter mode), this register contains the nonce value.
Reading this register while AES is enabled will return the value 0x00000000.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IVR3[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IVR3[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:0 IVR3[31:0]: Initialization vector register (MSB IVR[127:96])
This register must be written before the EN bit in the AES_CR register is set:
The register value has no meaning if:
– The ECB mode (electronic codebook) is selected.
– The CTR or CBC mode is selected in addition with the key derivation or key derivation + decryption
mode.
In CTR mode (counter mode), this register contains the nonce value.
Reading this register while AES is enabled will return the value 0x00000000.
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