To Next Page

To Previous Page

DocID024597 Rev 5 865/1830

RM0351 Hash processor (HASH)

875

29.6 HASH registers

The HASH core is associated with several control and status registers and five message

digest registers. All these registers are accessible through 32-bit word accesses only, else

an AHB2 error is generated.

29.6.1 HASH control register (HASH_CR)

Address offset: 0x00

Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ALGO[1] Res. LKEY

rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. MDMAT DINNE NBW ALGO[0] MODE DATATYPE DMAE INIT Res. Res.

rwrrrrrrwrwrwrwrww

Bits 31:19 Reserved, must be kept at reset value

Bit 18 ALGO[1]: refer to bit 7 description

Bit 17 Reserved, must be kept at reset value

Bit 16 LKEY: Long key selection

This bit selects between short key (≤ 64 bytes) or long key (> 64 bytes) in HMAC

mode.

0: Short key (≤ 64 bytes)

1: Long key (> 64 bytes)

Note: This selection is only taken into account when the INIT bit is set and

MODE= 1. Changing this bit during a computation has no effect.

Bit 15 Reserved, must be kept at reset value

Bit 14 Reserved, must be kept at reset value

Bit 13 MDMAT: Multiple DMA Transfers

This bit is set when hashing large files when multiple DMA transfers are needed.

0: DCAL is automatically set at the end of a DMA transfer.

1: DCAL is not automatically set at the end of a DMA transfer.

Bit 12 DINNE: DIN not empty

This bit is set when the HASH_DIN register holds valid data (that is after being

written at least once). It is cleared when either the INIT bit (initialization) or the

DCAL bit (completion of the previous message processing) is written to 1.

0: No data are present in the data input buffer

1: The input buffer contains at least one word of data

ST STM32L4 5 Series User Manual

Questions and Answers: