Intel Arria 10 - Page 109

Parameter Value
Enable tx_enh_fifo_pfull port On / Off
Enable tx_enh_fifo_empty port On / Off
Enable tx_enh_fifo_pempty port On / Off
RX FIFO mode Interlaken
RX FIFO partially full threshold from 10-29 (no less than pempty_threshold+8)
RX FIFO partially empty threshold 2 to 10
Enable RX FIFO alignment word deletion (Interlaken) On / Off
Enable RX FIFO control word deletion (Interlaken) On / Off
Enable rx_enh_data_valid port On / Off
Enable rx_enh_fifo_full port On / Off
Enable rx_enh_fifo_pfull port On / Off
Enable rx_enh_fifo_empty port On / Off
Enable rx_enh_fifo_pempty port On / Off
Enable rx_enh_fifo_del port (10GBASE-R) Off
Enable rx_enh_fifo_insert port (10GBASE-R) Off
Enable rx_enh_fifo_rd_en port On
Enable rx_enh_fifo_align_val port (Interlaken) On / Off
Enable rx_enh_fifo_align_clr port (Interlaken) On
Table 80. Interlaken Frame Generator Parameters
Parameter Value
Enable Interlaken frame generator On
Frame generator metaframe length 5 to 8192 (Intel recommends a minimum metaframe
length of 128)
Enable frame generator burst control On
Enable tx_enh_frame port On
Enable tx_enh_frame_diag_status port On
Enable tx_enh_frame_burst_en port On
Table 81. Interlaken Frame Synchronizer Parameters
Parameter Value
Enable Interlaken frame synchronizer On
Frame synchronizer metaframe length 5 to 8192 (Intel recommends a minimum metaframe
length of 128)
Enable rx_enh_frame port On
Enable rx_enh_frame_lock port On / Off
Enable rx_enh_frame_diag_status port On / Off
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
109