Intel Arria 10 User Manual

The IEEE 1588 Precision Time Protocol (PTP) is supported by the preset of the Arria 10
transceiver Native PHY that configures 10GBASE-R PHY IP in IEEE-1588v2 mode. PTP
is used for precise synchronization of clocks in applications such as:
• Distributed systems in telecommunications
• Power generation and distribution
• Industrial automation
• Robotics
• Data acquisition
• Test equipment
• Measurement
The protocol is applicable to systems communicating by local area networks including,
but not limited to, Ethernet. The protocol enables heterogeneous systems that include
clocks of various inherent precision, resolution, and stability to synchronize to a
grandmaster clock.
Figure 56. Transceiver Channel Datapath and Clocking for 10GBASE-R with IEEE 1588v2
Transmitter Enhanced PCSTransmitter PMA
Receiver PMA
Receiver Enhanced PCS
TX
Gearbox
tx_serial_data
Serializer
Interlaken
Disparity Generator
Scrambler
(self sync) mode
Parallel Clock
PRBS
Generator
PRP
Generator
rx_serial_data
Deserializer
CDR
Descrambler
Interlaken
Disparity Checker
Block
Synchronizer
Interlaken
Frame Sync
RX
Gearbox
PRBS
Verifier
Transcode
Decoder
KR FEC RX
Gearbox
KR FEC
Decoder
KR FEC
Block Sync
KR FEC
Descrambler
Parallel Clock
Parallel Clock
Serial Clock
Parallel and Serial Clocks
Clock Divider
Parallel and Serial Clocks
Clock Generation Block (CGB)
Serial Clock
Input Reference Clock
ATX PLL
fPLL
CMU PLL
64B/66B Decoder
and RX SM
10GBASE-R
BER Checker
PRP
rx_pma_div_clkout
tx_pma_div_clkout
Verifier
rx_coreclkin
rx_clkout
Register Mode
Interlaken
Frame Generator
Interlaken
CRC32 Generator
Interlaken
CRC32 Checker
64B/66B Encoder
and TX SM
FPGA
Fabric
tx_coreclkin
tx_clkout
KR FEC
TX Gearbox
KR FEC
Scrambler
KR FEC
Encoder
Transcode
Encoder
10.3125 Gbps
5156.25 MHz (data rate/2) (1)
Notes:
1. Value based on the clock division factor chosen.
2. Value calculated as data rate / PCS-PMA interface width.
40
66
@ 257.8125 MHz (2)
TX XGMII
@ 156.25 MHz
RX XGMII
@ 156.25 MHz
@ 257.8125 MHz (2)
40
66
64
64
Soft Phase
Compensation
FIFO
Soft Clock
Compensation
FIFO
64 (data) + 8 (control)
Register Mode
64 (data) + 8 (control)
10GBASE-R with FEC
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
126

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex