Intel Arria 10 User Manual

Arria 10 10GBASE-R has the optional FEC variant that also targets the 10GBASE-KR
PHY. This provides a coding gain to increase the link budget and BER performance on
a broader set of backplane channels as defined in Clause 69. It provides additional
margin to account for variations in manufacturing and environment conditions. The
additional TX FEC sublayer:
• Receives data from the TX PCS
• Transcodes 64b/66b words
• Performs encoding/framing
• Scrambles and sends the FEC data to the PMA
The RX FEC sublayer:
• Receives data from the PMA
• Performs descrambling
• Achieves FEC framing synchronization
• Decodes and corrects data where necessary and possible
• Recodes 64b/66b words and sends the data to the PCS
The 10GBASE-R with KR FEC protocol is a KR FEC sublayer placed between the PCS
and PMA sublayers of the 10GBASE-R physical layer.
Figure 57. Transceiver Channel Datapath and Clocking for 10GBASE-R with KR FEC
Transmitter Enhanced PCSTransmitter PMA
Receiver PMA
Receiver Enhanced PCS
TX
Gearbox
tx_serial_data
Serializer
Interlaken
Disparity Generator
Scrambler
Parallel Clock (161.1 MHz) (3)
tx_pma_clk
tx_krfec_clk
PRBS
Generator
PRP
Generator
rx_serial_data
Deserializer
CDR
Descrambler
Interlaken
Disparity Checker
Block
Synchronizer
Interlaken
Frame Sync
RX
Gearbox
PRBS
Verifier
Transcode
Decoder
KR FEC RX
Gearbox
KR FEC
Decoder
KR FEC
Block Sync
KR FEC
Descrambler
Parallel Clock (161.1 MHz) (3)
rx_pma_clk
rx_krfec_clk
Parallel Clock
Serial Clock
Parallel and Serial Clocks
Clock Divider
Parallel and Serial Clocks
Clock Generation Block (CGB)
Serial Clock
rx_rcvd_clk
tx_hf_clk
tx_serial_clk0
(5156.25 MHz) =
Data rate/2
Input Reference Clock
ATX PLL
fPLL
CMU PLL
64B/66B Decoder
and RX SM
10GBASE-R
Notes:
1. Value is based on the clock division factor chosen
2. Value is calculated as data rate/FPGA fabric - PCS interface width
3. Value is calculated as data rate/PCS-PMA interface width
4. For 10GBASE-R with KR FEC, TX FIFO is in phase compensation mode
5. For 10GBASE-R with KR FEC, RX FIFO is in 10GBASE-R mode
BER Checker
PRP
rx_pma_div_clkout
tx_pma_div_clkout
Verifier
rx_coreclkin
rx_clkout
Enhanced PCS
TX FIFO
(4)
Enhanced PCS
RX FIFO
(5)
Interlaken
Frame Generator
Interlaken
CRC32 Generator
Interlaken
CRC32 Checker
64B/66B Encoder
and TX SM
TX
Data &
Control
FPGA
Fabric
tx_coreclkin
tx_clkout
KR FEC
TX Gearbox
KR FEC
Scrambler
KR FEC
Encoder
Transcode
Encoder
KR FEC
KR FEC
64
66
64
64
@ 156.25 MHz
from XGMII
@ 156.25 MHz
from XGMII
64 + 8
RX
Data &
Control
64 + 8
5156.25 MHz (data rate/2) (1)
The CMU PLL or the ATX PLLs generate the TX high speed serial clock.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
127

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex