6. Create a transceiver reset controller. You can use your own reset controller or use
the Arria 10 Transceiver Native PHY Reset Controller IP.
7. Connect the Arria 10 Transceiver Native PHY to the PLL IP and the reset controller.
Figure 61. Connection Guidelines for a 10GBASE-R or 10GBASE-R with FEC PHY Design
Reset
Controller
Arria 10 Transceiver
Native PHY
To MAC/RS
through XGMII
Interface
64d + 8c
PLL IP
Medium
Figure 62. Connection Guidelines for a 10GBASE-R with IEEE 1588v2 PHY Design
Reset
Controller
To MAC/RS
through XGMII
Interface
64d + 8c
64d + 8c
FIFO in the
FPGA core
for TX
FIFO in the
FPGA core
for RX
PLL IP
Medium
Arria 10 Transceiver
Native PHY
8. Simulate your design to verify its functionality.
Related Information
• Arria 10 Enhanced PCS Architecture on page 461
For more information about Enhanced PCS architecture
• Arria 10 PMA Architecture on page 447
For more information about PMA architecture
• Using PLLs and Clock Networks on page 398
For more information about implementing PLLs and clocks
• PLLs on page 349
PLL architecture and implementation details
• Resetting Transceiver Channels on page 416
Reset controller general information and implementation details
• Enhanced PCS Ports on page 76
For detailed information about the available ports in the 10GBASE-R 1588
protocol.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
131