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Intel Arria 10 User Manual

Intel Arria 10
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6. Create a transceiver reset controller. You can use your own reset controller or use
the Arria 10 Transceiver Native PHY Reset Controller IP.
7. Connect the Arria 10 Transceiver Native PHY to the PLL IP and the reset controller.
Figure 61. Connection Guidelines for a 10GBASE-R or 10GBASE-R with FEC PHY Design
Reset
Controller
Arria 10 Transceiver
Native PHY
To MAC/RS
through XGMII
Interface
64d + 8c
PLL IP
Medium
Figure 62. Connection Guidelines for a 10GBASE-R with IEEE 1588v2 PHY Design
Reset
Controller
To MAC/RS
through XGMII
Interface
64d + 8c
64d + 8c
FIFO in the
FPGA core
for TX
FIFO in the
FPGA core
for RX
PLL IP
Medium
Arria 10 Transceiver
Native PHY
8. Simulate your design to verify its functionality.
Related Information
Arria 10 Enhanced PCS Architecture on page 461
For more information about Enhanced PCS architecture
Arria 10 PMA Architecture on page 447
For more information about PMA architecture
Using PLLs and Clock Networks on page 398
For more information about implementing PLLs and clocks
PLLs on page 349
PLL architecture and implementation details
Resetting Transceiver Channels on page 416
Reset controller general information and implementation details
Enhanced PCS Ports on page 76
For detailed information about the available ports in the 10GBASE-R 1588
protocol.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
131

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Intel Arria 10 Specifications

General IconGeneral
Transceiver Data RateUp to 17.4 Gbps
Transceiver Protocols SupportedCPRI, JESD204B
Transceiver Power ConsumptionVaries depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver FeaturesClock data recovery
Power Consumption per ChannelVaries depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver TypeFPGA integrated transceiver
Operating Temperature Range-40°C to 100°C (Industrial)
Number of Transceiver Channelsup to 96 full-duplex

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