Intel Arria 10 User Manual

2.6.2.2. How to Implement 10GBASE-R, 10GBASE-R with IEEE 1588v2, and
10GBASE-R with FEC in Arria 10 Transceivers
You should be familiar with the 10GBASE-R and PMA architecture, PLL architecture,
and the reset controller before implementing the 10GBASE-R, 10GBASE-R with IEEE
1588v2, or 10GBASE-R with FEC Transceiver Configuration Rules.
You must design your own MAC and other layers in the FPGA to implement the
10GBASE-R, 10GBASE-R with 1588, or 10GBASE-R with KR FEC Transceiver
Configuration Rule using the Native PHY IP.
1. Instantiate the Arria 10 Transceiver Native PHY IP from the IP Catalog.
Refer to Select and Instantiate the PHY IP Core on page 33 for more details.
2. Select 10GBASE-R, 10GBASE-R 1588, or 10GBASE-R with KR FEC from the
Transceiver configuration rule list located under Datapath Options,
depending on which protocol you are implementing.
3. Use the parameter values in the tables in Transceiver Native PHY Parameters for
the 10GBASE-R Protocol as a starting point. Or, you can use the protocol presets
described in Transceiver Native PHY Presets. Select 10GBASE-R Register Mode
for 10GBASE-R with IEEE 1588v2. You can then modify the settings to meet
your specific requirements.
4. Click Generate to generate the Native PHY IP core RTL file.
Figure 60. Signals and Ports of Native PHY IP Core for the 10GBASE-R, 10GBASE-R with
IEEE 1588v2, and 10GBASE-R with FEC
Generating the IP core creates signals and ports based on your parameter settings.
reconfig_reset
reconfig_clk
reconfig_avmm
tx_digitalreset
xgmii_tx_c[7:0] (2)
xgmii_tx_d[63:0] (2)
xgmii_tx_clk
1’b1 (1)
tx_control[17:0]
tx_parallel_data[127:0]
tx_coreclkin
tx_clkout
tx_enh_data_valid
tx_fifo_flags
Reconfiguration
Registers
TX Enhanced PCS
rx_clkout
rx_coreclkin
rx_enh_blk_lock
rx_enh_highber
rx_fifo_flags
RX Enhanced PCS
Nios Hard
Calibration IP
TX PMA
Serializer
RX PMA
DeserializerCDR
tx_cal_busy
rx_cal_busy
tx_serial_data
rx_serial_data
rx_parallel_data[127:0]
rx_control[19:0]
rx_cdr_refclk0
rx_is_lockedtodata
rx_is_lockedtoref
Clock
Generation
Block
tx_serial_clk0 (from TX PLL)
tx_analogreset
rx_analogreset
rx_digitalreset
xgmii_rx_clk
Arria 10 Transceiver Native PHY
Notes:
1. For 10GBASE-R with 1588 configurations, this signal is user-controlled.
2. For 10GBASE-R with 1588 configurations, this signal is connected from the output of TX FIFO in the FPGA fabric.
5. Instantiate and configure your PLL.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
130

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex