Intel Arria 10 User Manual

Table 117. RX XGMII Mapping to Standard SDR XGMII Interface
The 72-bit RX XGMII data bus format is different from the standard SDR XGMII interface. This table shows the
mapping of this non-standard format to the standard SDR XGMII interface.
Signal Name XGMII Signal Name Description
xgmii_rx_dc[7:0] xgmii_sdr_data[7:0]
Lane 0 data
xgmii_rx_dc[8] xgmii_sdr_ctrl[0]
Lane 0 control
xgmii_rx_dc[16:9] xgmii_sdr_data[15:8]
Lane 1 data
xgmii_rx_dc[17] xgmii_sdr_ctrl[1]
Lane 1 control
xgmii_rx_dc[25:18] xgmii_sdr_data[23:16]
Lane 2 data
xgmii_rx_dc[26] xgmii_sdr_ctrl[2]
Lane 2 control
xgmii_rx_dc[34:27] xgmii_sdr_data[31:24]
Lane 3 data
xgmii_rx_dc[35] xgmii_sdr_ctrl[3]
Lane 3 control
xgmii_rx_dc[43:36] xgmii_sdr_data[39:32]
Lane 4 data
xgmii_rx_dc[44] xgmii_sdr_ctrl[4]
Lane 4 control
xgmii_rx_dc[52:45] xgmii_sdr_data[47:40]
Lane 5 data
xgmii_rx_dc[53] xgmii_sdr_ctrl[5]
Lane 5 control
xgmii_rx_dc[61:54] xgmii_sdr_data[55:48]
Lane 6 data
xgmii_rx_dc[62] xgmii_sdr_ctrl[6]
Lane 6 control
xgmii_rx_dc[70:63] xgmii_sdr_data[63:56]
Lane 7 data
xgmii_rx_dc[71] xgmii_sdr_ctrl[7]
Lane 7 control
2.6.3.5.4. Serial Data Interface
Table 118. Serial Data Signals
Signal Name Direction Description
rx_serial_data
Input RX serial input data
tx_serial_data
Output TX serial output data
2.6.3.5.5. Control and Status Interfaces
Table 119. Control and Status Signals
Signal Name Direction Clock Domain Description
led_link
Output Synchronous to
tx_clkout
When asserted, indicates successful link synchronization.
led_disp_err
Output Synchronous to
rx_clkout
Disparity error signal indicating a 10-bit running disparity
error. Asserted for one rx_clkout_1g cycle when a
disparity error is detected. A running disparity error
indicates that more than the previous and perhaps the
current received group had an error.
led_an
Output Synchronous to
rx_clkout
Clause 37 Auto-negotiation status. The PCS function
asserts this signal when auto-negotiation completes.
continued...
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
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Arria
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10 Transceiver PHY User Guide
146

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex