Intel Arria 10 User Manual

Figure 14. GT Transceiver Bank Architecture
In the GT device, the transceiver banks GXBL1E, GXBL1G, and GXBL1H include GT channels.
CH1
PMA
Channel PLL
(CDR Only)
PCS
Local CGB5
CH5
PMA
Channel PLL
(CMU/CDR)
PCS
Local CGB4
CH4
PMA
Channel PLL
(CDR Only)
PCS
Local CGB3
CH3
PMA
Channel PLL
(CDR Only)
PCS
Local CGB2
CH2
PMA
Channel PLL
(CMU/CDR)
PCS
Local CGB1
PMA
Channel PLL
(CDR Only)
PCS
Local CGB0
CH0
FPGA Core
Fabric
Clock
Distribution
Network
Six-Channel GT Transceiver Bank GXBL1G
fPLL1
Master
CGB1
Master
CGB0
ATX
PLL1
ATX
PLL0
fPLL0
GX Channel
GT/GX Channel
Legend
Note: This figure is a high level overview of the transceiver bank architecture. For details
about the available clock networks refer to the PLLs and Clock Networks chapter.
1. Arria
®
10 Transceiver PHY Overview
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
23

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex