Intel Arria 10 User Manual

Table 207. RX PMA Parameters
Parameter Value
Number of CDR reference clocks 1
Selected CDR reference clock 0
Selected CDR reference clock frequency Select legal range defined by the Quartus Prime
software
PPM detector threshold 1000
CTLE adaptation mode manual
DFE adaptation mode disabled
Number of fixed dfe taps 3
Enable rx_pma_clkout port Off
Enable rx_pma_div_clkout port On
rx_pma_div_clkout division factor 2
Enable rx_pma_clkslip port Off
Enable rx_pma_qpipulldn port (QPI) Off
Enable rx_is_lockedtodata port On
Enable rx_is_lockedtoref port On
Enable rx_set_locktodata and rx_set_locktoref ports Off
Enable rx_seriallpbken port Off
Enable PRBS verifier control and status ports Off
Table 208. Standard PCS Parameters
Parameters Value
Standard PCS / PMA interface width 20
FPGA fabric / Standard TX PCS interface width 32
FPGA fabric / Standard RX PCS interface width 32
Enable 'Standard PCS' low latency mode Off
TX FIFO mode register_fifo
RX FIFO mode register_fifo
Enable tx_std_pcfifo_full port Off
Enable tx_std_pcfifo_empty port Off
Enable rx_std_pcfifo_full port Off
Enable rx_std_pcfifo_empty port Off
TX byte serializer mode Serialize x2
RX byte deserializer mode Deserialize x2
Enable TX 8B/10B encoder On
Enable TX 8B/10B disparity control Off
Enable RX 8B/10B decoder On
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2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex