Intel Arria 10 User Manual

Parameters Value
RX rate match FIFO mode Disabled
RX rate match insert / delete -ve pattern (hex)
0x00000000
RX rate match insert / delete +ve pattern (hex)
0x00000000
Enable rx_std_rmfifo_full port Off
Enable rx_std_rmfifo_empty port Off
PCI Express Gen3 rate match FIFO mode Bypass
Enable TX bit slip Off (CPRI Auto configuration)
On (CPRI Manual configuration)
Enable tx_std_bitslipboundarysel port Off (CPRI Auto configuration)
On (CPRI Manual configuration)
RX word aligner mode deterministic latency (CPRI Auto
configuration)
manual (FPGA fabric controlled) (CPRI
Manual configuration)
RX word aligner pattern length 10
RX word aligner pattern (hex)
0x000000000000017c
Number of word alignment patterns to achieve sync 3
(47)
Number of invalid data words to lose sync 3
(47)
Number of valid data words to decrement error count 3
(47)
Enable fast sync status reporting for deterministic latency SM On / Off
Enable rx_std_wa_patternalign port On / Off
Enable rx_std_wa_a1a2size port Off
Enable rx_std_bitslipboundarysel port Off (CPRI Auto configuration)
On (CPRI Manual configuration)
Enable rx_bitslip port Off (CPRI Auto configuration)
On (CPRI Manual configuration)
All options under Bit Reversal and Polarity Inversion Off
All options under PCIe Ports Off
Table 209. Dynamic Reconfiguration
Parameter Value
Enable dynamic reconfiguration Off
Share reconfiguration interface Off
Enable Altera Debug Master Endpoint Off
Enable embedded debug Off
Enable capability registers Off
Set user-defined IP identifier 0
continued...
(47)
These are unused when the transceiver PHY is in CPRI mode.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
288

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex