The RX bit slip feature is optional and may or may not be enabled.
Figure 137. RX Bit Slip in 8-bit Mode
tx_parallel_data = 8'hbc
rx_std_bitslipboundarysel
rx_bitslip
tx_parallel_data
rx_parallel_data
01111
bc
00 97 cb e5 f2 79 bc
Figure 138. RX Bit Slip in 10-bit Mode
tx_parallel_data = 10'h3bc
000 1de 0ef 277 33b 39d
3bc
01111rx_std_bitslipboundarysel
rx_bitslip
tx_parallel_data
rx_parallel_data 3ce 1e7 2f3 379 3bc
Figure 139. RX Bit Slip in 16-bit Mode
tx_parallel_data = 16'hfcbc
979f cbcf e5e7 f2f3 f979 fcbc
fcbc
rx_std_bitslipboundarysel
rx_bitslip
tx_parallel_data
rx_parallel_data
00001 00010 00011 00100 00101 00110
Figure 140. RX Bit Slip in 20-bit Mode
tx_parallel_data = 20'h3fcbc
3fcbc
rx_std_bitslipboundarysel
rx_bitslip
tx_parallel_data
rx_parallel_data
00001 00010 00011 00100 00101 00110 00111 01000
e5e1f f2f0f f9787 fcbc3 de5e1 ff2f0 7f978 3fcbc
2.9.2.4. RX Polarity Inversion
Receiver polarity inversion can be enabled in low latency, basic, and basic rate match
modes.
To enable the RX polarity inversion feature, select the Enable RX polarity inversion
and Enable rx_polinv port options.
This mode adds rx_polinv. If there is more than one channel in the design,
rx_polinv is a bus in which each bit corresponds to a channel. As long as
rx_polinv is asserted, the RX data received has a reverse polarity.
You can verify this feature by monitoring rx_parallel_data.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
305