Intel Arria 10 User Manual

Resetting the Transceiver in CDR Manual Lock Mode
The numbers in this list correspond to the numbers in the following figure, which
guides you through the steps to put the CDR in manual lock mode.
1.
Make sure that the calibration is complete (rx_cal_busy is low) and the
transceiver goes through the initial reset sequence. The rx_digitalreset and
rx_analogreset signals should be low. The rx_is_lockedtoref is a don't
care and can be either high or low. The rx_is_lockedtodata and rx_ready
signals should be high, indicating that the transceiver is out of reset. Alternatively,
you can start directly with the CDR in manual lock mode after the calibration is
complete.
2.
Assert the rx_set_locktoref signal high to switch the CDR to the lock-to-
reference mode. The rx_is_lockedtodata status signal is deasserted. Assert
the rx_digitalreset signal high at the same time or after
rx_set_lockedtoref is asserted if you use the user-coded reset. When the
Transceiver PHY reset controller is used, the rx_digitalreset is automatically
asserted.
3.
After the rx_digitalreset signal gets asserted, the rx_ready status signal is
deasserted.
4.
Assert the rx_set_locktodata signal high, t
LTR_LTD_Manual
(minimum 15 μs)
after the CDR is locked to reference. rx_is_locktoref should be high and
stable for a minimum t
LTR_LTD_Manual
(15 μs), before asserting
rx_set_locktodata. This is required to filter spurious glitches on
rx_is_lockedtoref. The rx_is_lockedtodata status signal gets asserted,
which indicates that the CDR is now set to LTD mode.
The rx_is_lockedtoref status signal can be a high or low and can be ignored
after asserting rx_set_locktodata high after the CDR is locked to reference.
5.
Deassert the rx_digitalreset signal after a minimum of t
LTD_Manual
(4 μs).
6.
If you are using the Transceiver PHY Reset Controller, the rx_ready status signal
gets asserted after the rx_digitalreset signal is deasserted. This indicates
that the receiver is now ready to receive data with the CDR in manual mode.
4. Resetting Transceiver Channels
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex