Intel Arria 10 User Manual

Figure 204. Reset Sequence Timing Diagram for Receiver when CDR is in Manual Lock
Mode
rx_digitalreset
rx_set_locktoref
rx_set_locktodata
rx_is_lockedtoref
rx_is_lockedtodata
rx_analogreset
rx_ready
Status Signals
Control Signals
1
2
2
4
5
6
3
1
1
1
1
2
4
4
rx_cal_busy
LTR_LTD_Manual
t
LTD_Manual
t
4.3.1.1.3. Resetting the Transceiver Channel During Device Operation
The numbers in this list correspond to the numbers in the following figure.
1.
Assert tx_analogreset, pll_powerdown, tx_digitalreset,
rx_analogreset, and rx_digitalreset. Ensure that pll_cal_busy,
tx_cal_busy, and rx_cal_busy are low.
2.
Deassert pll_powerdown and tx_analogreset at the same time, after a
minimum duration of 70 μs.
3.
The pll_locked signal goes high after the TX PLL acquires lock. Wait for a
minimum 70 μs after deasserting tx_analogreset to monitor the pll_locked
signal.
4.
Deassert tx_digitalreset after pll_locked goes high. The
tx_digitalreset signal must stay asserted for a minimum t
tx_digitalreset
(minimum of 70 μs) duration after tx_analogreset is deasserted.
5.
Deassert rx_analogreset after deasserting tx_analogreset.
6.
Ensure rx_is_lockedtodata is asserted for t
LTD
(minimum of 4 μs) before
deasserting rx_digitalreset.
4. Resetting Transceiver Channels
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
424

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex