The DFE advantage over CTLE is improved Signal to Noise Ratio (SNR). DFE amplifies
the power of the high frequency components without amplifying the noise power.
Figure 229. Signal ISI
ISI+
ISI-
Precursor Cursor Postcursor
Notes:
• An ideal pulse response is a single data point at the cursor.
• Real world pulse response is non-zero before the cursor (precursor) and after the
cursor (postcursor).
• ISI occurs when the data sampled at precursor or postcursor is not zero.
The DFE circuit stores delayed versions of the data. The stored bit is multiplied by a
coefficient and then summed with the incoming signal. The polarity of each coefficient
is programmable.
The DFE architecture supports eleven fixed taps.
The eleven fixed taps translate to the DFE capable of removing the ISI from the next
11 bits, beginning from the current bit.
5. Arria 10 Transceiver PHY Architecture
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
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