1. Request user access to the internal configuration bus by writing 0x0 to offset
address 0x0[7:0].
2.
Monitor and wait for avmm_waitrequest to be deasserted (logic low) if "Separate
reconfig_waitrequest from PreCISE" option is disabled. Otherwise, monitor
and wait for register bit 0x281 bit[2] to go low if "Separate
reconfig_waitrequest from PreCISE" and "Enable control and status
registers" option is enabled.
3. Select adaptation control by Read-Modify-Write 0x1 to bit[4] of address 0x149.
4. Enable adaptation trigger by Read-Modify-Write 0x1 to bit[6] of address 0x100.
5. Release the internal configuration bus to PreSICE by writing 0x1 to offset address
0x0[7:0].
6. Repeat step 2.
7. Monitor DFE adaptation completion by checking register bit 0x100 bit[6] to go low.
This confirms DFE trigger adaptation routine is complete.
Related Information
Analog Parameter Settings on page 585
Configuration Methods
Configure the modes using one of the following methods:
Method 1 - Using Arria 10 Transceiver Native PHY IP Core
1. Select the CTLE/DFE mode in the RX PMA tab of the PHY IP Core
2. Compile the design
3. Choose one the following:
• If CTLE or DFE is in Manual mode, set the CTLE gain value or DFE taps using
one of the following ways:
a. Assignment Editor/.qsf- Recompile the design to make these values
effective.
Refer to Analog Parameter Settings for more details about Receiver
Equalization Settings.
b. Avalon-MM (AVMM) Interface - Value written through AVMM interface take
precedence over values defined in Assignment Editor. Use this method to
dynamically set values and hence avoid re-compilation.
Refer to Arria 10 Transceiver Register Map for more details on AVMM
interface and to perform dynamic read/write.
Method 2 - Using AVMM Interface
1. Any changes you make using AVMM interface take precedence over what was
configured in Native PHY IP GUI and/or Assignment Editor.
a. For CTLE and DFE in Manual mode, set the CTLE gain value or DFE Taps using
the reconfiguration interface. The values are written dynamically and do not
require design re-compilation.
5. Arria 10 Transceiver PHY Architecture
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
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