Intel Arria 10 User Manual

5.2.2.2. Block Synchronizer
The block synchronizer determines the block boundary of a 66-bit word in the case of
the 10GBASE-R protocol or a 67-bit word in the case of the Interlaken protocol. The
incoming data stream is slipped one bit at a time until a valid synchronization header
(bits 65 and 66) is detected in the received data stream. After the predefined number
of synchronization headers (as required by the protocol specification) is detected, the
block synchronizer asserts rx_enh_blk_lock (block lock status signal) to other
receiver PCS blocks down the receiver datapath and to the FPGA fabric.
Note: The block synchronizer is designed in accordance with Interlaken Protocol specification
(as described in Figure 13 of Interlaken Protocol Definition v1.2) and 10GBASE-R
protocol specification (as described in IEEE 802.3-2008 clause-49).
5.2.2.3. Interlaken Disparity Checker
The Interlaken disparity checker examines the received inversion bit inserted by the
far end disparity generator, to determine whether to reverse the inversion process of
the Interlaken disparity generation.
Note: The Interlaken disparity checker is available to implement the Interlaken protocol.
5.2.2.4. Descrambler
The descrambler block descrambles received data to regenerate unscrambled data
using the x
58
+ x
39
+1 polynomial. Like the scrambler, it operates in asynchronous
mode or synchronous mode.
Related Information
Scrambler on page 468
5.2.2.5. Interlaken Frame Synchronizer
The Interlaken frame synchronizer delineates the metaframe boundaries and searches
for each of the framing layer control words: Synchronization, Scrambler State, Skip,
and Diagnostic. When four consecutive synchronization words have been identified,
the frame synchronizer achieves the frame locked state. Subsequent metaframes are
then checked for valid synchronization and scrambler state words. If four consecutive
invalid synchronization words or three consecutive mismatched scrambler state words
are received, the frame synchronizer loses frame lock. In addition, the frame
synchronizer provides rx_enh_frame_lock (receiver metaframe lock status) to the
FPGA fabric.
Note: The Interlaken frame synchronizer is available to implement the Interlaken protocol.
5.2.2.6. 64B/66B Decoder and Receiver State Machine (RX SM)
The 64B/66B decoder reverses the 64B/66B encoding process. The decoder block also
contains a state machine (RX SM) designed in accordance with the IEEE802.3-2008
specification. The RX SM checks for a valid packet structure in the data sent from the
remote side. It also performs functions such as sending local faults to the Media
Access Control (MAC)/Reconciliation Sublayer (RS) under reset and substituting error
codes when the 10GBASE-R and 10GBASE-KR PCS rules are violated.
Note:
The 64B/66B decoder is available to implement the 10GBASE-R protocol.
5. Arria 10 Transceiver PHY Architecture
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex