Intel Arria 10 User Manual

5.3.2.1.5. Word Aligner Pattern Length for Various Word Aligner Modes
Table 261. Word Aligner Pattern Length for Various Word Aligner Modes
PCS-PMA
Interface
Width
Supported Word
Aligner Modes
Supported
Word Aligner
Pattern
Lengths
rx_std_wa_patte
rnalign behavior
rx_syncstatus
behavior
rx_patterndetect
behavior
8 Bit slip 8
rx_std_wa_patt
ernalign has no
effect on word
alignment. The
single width word
aligner updates the
word boundary,
only when the
FPGA fabric-
asserted BITSLIP
signal toggles.
N/A N/A
Manual 8, 16 Word alignment is
controlled by
rx_std_wa_patt
ernalign and is
edge-sensitive to
this signal.
Asserted high for
one parallel clock
cycle when the
word aligner aligns
to a new boundary.
Asserted high for
one parallel clock
cycle when the word
alignment pattern
appears in the
current word
boundary.
10 Bit slip 7
rx_std_wa_patt
ernalign has no
effect on word
alignment. The
single width word
aligner updates the
word boundary,
only when the
FPGA fabric-
asserted BITSLIP
signal toggles.
N/A N/A
Manual 7, 10 Word alignment is
controlled by
rx_std_wa_patt
ernalign and is
level-sensitive to
this signal.
Asserted high for
one parallel clock
cycle when the
word aligner aligns
to a new boundary.
Asserted high for
one parallel clock
cycle when the word
alignment pattern
appears in the
current word
boundary.
Deterministic latency
(CPRI mode only)
10 Word alignment is
controlled by
rx_std_wa_patt
ernalign (edge-
sensitive to this
signal) and the
state machine
works in
conjunction with
PMA to achieve
deterministic
latency on the RX
path for CPRI and
OBSAI applications.
—
—
Synchronous State
Machine
7, 10
rx_std_wa_patt
ernalign has no
effect on word
alignment.
Stays high as long
as the
synchronization
conditions are
satisfied.
Asserted high for
one parallel clock
cycle when the word
alignment pattern
continued...
5. Arria 10 Transceiver PHY Architecture
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
488

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex