PCS-PMA
Interface
Width
Supported Word
Aligner Modes
Supported
Word Aligner
Pattern
Lengths
rx_std_wa_patte
rnalign behavior
rx_syncstatus
behavior
rx_patterndetect
behavior
appears in the
current word
boundary.
16 Bit slip 16
rx_std_wa_patt
ernalign has no
effect on word
alignment. The
double width word
aligner updates the
word boundary,
only when the
FPGA fabric-
asserted BITSLIP
signal toggles.
N/A N/A
Manual 8, 16, 32 Word alignment is
controlled by
rising-edge of
rx_std_wa_patt
ernalign.
Stays high after
the word aligner
aligns to the word
alignment pattern.
Goes low on
receiving a rising
edge on
rx_std_wa_patt
ernalign until a
new word
alignment pattern
is received.
Asserted high for
one parallel clock
cycle when the word
alignment pattern
appears in the
current word
boundary.
20 Bit slip 7
rx_std_wa_patt
ernalign has no
effect on word
alignment. The
double width word
aligner updates the
word boundary,
only when the
FPGA fabric-
asserted BITSLIP
signal toggles.
N/A N/A
Manual 7, 10, 20, 40 Word alignment is
controlled by rising
edge of
rx_std_wa_patt
ernalign.
Stays high after
the word aligner
aligns to the word
alignment pattern.
Goes low on
receiving a rising
edge on
rx_std_wa_patt
ernalign until a
new word
alignment pattern
is received.
Asserted high for
one parallel clock
cycle when the word
alignment pattern
appears in the
current word
boundary.
Deterministic latency
(CPRI mode only)
10 Word alignment is
controlled by
rx_std_wa_patt
ernalign (edge-
sensitive to this
signal) and the
deterministic
latency state
machine which
controls the PMA to
—
—
continued...
5. Arria 10 Transceiver PHY Architecture
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
489
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