Intel Arria 10 User Manual

Reconfiguratio
n Address
(HEX)
Reconfiguratio
n Bit
Attribute Name Related
Addresses
Attribute
Encoding
Bit
Encoding
Description
prbs_9 4'b0010 Enable PRBS9 pattern
prbs_15 4'b0100 Enable PRBS15
pattern
prbs_23 4'b1000 Enable PRBS23
pattern
prbs_31 4'b0000 Enable PRBS31
pattern
0x00C [0] prbs_ver 0xB prbs_7 1'b0 Enable PRBS7 pattern
prbs_9 1'b0 Enable PRBS9 pattern
prbs_15 1'b0 Enable PRBS15
pattern
prbs_23 1'b0 Enable PRBS23
pattern
prbs_31 1'b1 Enable PRBS31
pattern
[3] prbs9_dwidth prbs9_10b 1'b1 PRBS9 10-bit
prbs9_64b 1'b0 PRBS9 64-bit
0x13F [3:0] deser_factor 10 4'b0001 10-bit mode
64 4'b1110 64-bit mode
Related Information
PRBS Soft Accumulators on page 547
6.16.1.1. Enabling the PRBS Data Generator in non bonded designs
You must perform a sequence of read-modify-writes to addresses 0x006, 0x007,
0x008, and 0x110 to enable either the PRBS data generator. To enable either the
PRBS data generator, follow these steps:
1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic
Reconfiguration.
2. Perform a read-modify-write to address 0x006 according to Register Map for PRBS
Generators for bonded and non bonded designs.
3. Perform a read-modify-write to address 0x007 according to Register Map for PRBS
Generators for bonded and non bonded designs.
4. Perform a read-modify-write to address 0x008 according to Register Map for PRBS
Generators for bonded and non bonded designs.
5. Perform a read-modify-write to address 0x110 with the specified width. This data
width is either 64-bit or 10-bit.
6. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic
Reconfiguration.
To disable the PRBS generator, write the original values back into the read-modify-
write addresses in Register Map for PRBS Generators for bonded and non bonded
designs.
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
553

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex