Keysight M8000 Series of BER Test Solutions User Guide 51
Know Your Hardware 2
M8062A 32Gb/s Front-end for J-BERT M8020A High-Performance BERT
The M8062A extends the data rate of the J-BERT M8020A Bit Error Ratio
Tester to the speeds required for testing devices with lane rates in the
25-28 Gb/s range. When combined with a two channel M8041A, the
system provides data pattern generation and full-rate error analysis for
users and systems with lane rates up to 32.4 Gb/s.
M8062A Features
• Extends maximum data rate of J-BERT M8020A up to 32.4 Gb/s
• Seamless control of pattern generator and error analyzer
• Integrated 8-tap de-emphasis
• Built in ISI generator for channel emulation
• Analyzer equalization eliminates errors resulting from closed eyes in
loop back path
• Built in CDR for data rates up to 32 Gb/s
Refer to the Online Help installed and integrated into the M8070A
software to learn about how to use this module.
The CDR license (M8062A-0A4) is required to enable the CDR feature.
M8062A modules with serial numbers < MY55400300 may also require a
hardware upgrade in order to enable this feature.
Phase-matched cables must be used when connecting the M8041A data
and clock outputs to the M8062A data and clock inputs. The provided
cable set, Keysight M8062-61643, meets this requirement.
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